The invention relates generally to devices that execute a plurality of different instruction sets and more particularly to methods and apparatus for providing instruction branch prediction for a plurality of different instruction sets.
Many microprocessors and other instruction execution devices employ some type of branch prediction to determine whether an instruction that has been fetched requires that the processor jump, or branch, to another address to obtain the next instruction to be fetched. Many microprocessors and other devices employ pipeline structures used to fetch, decode, execute and commit each instruction. In addition, processors are known that employ variable length instruction sets, such as Intel(copyright) X.86 family of microprocessors. Also, processors are known that execute different instruction sets, such as a variable length instruction set (e.g., X.86 type instructions) and another instruction set such as fixed length RISC instruction sets.
With branch prediction, there are different types of branches, such as unconditional branches and conditional branches. An unconditional branch, for example, may require that a processor always jump to a same address. Alternatively, a conditional branch may only require that a branch be taken if certain conditions are met and jump to a same address.
With pipeline based instruction execution, if there is a branch, the branch will not be known until after the operational code or command has been decoded. Filling the pipeline with the branch target address requires flushing the pipeline so that the branch address is the next address to be executed. It is desired to keep the pipeline filled since when commands are fetched, the branches are not typically known, nor which directions they may go. After decoding, when the system knows that a branch is necessary in the case of unconditional and after executing in the case of conditional, it may know which direction the branch is going, namely, in a taken/not taken direction to indicate which address needs to be examined next. As such, fetch based branch prediction is used to attempt to predict what the next address to fetch should be before branch decoding and execution.
Branch prediction can find increased advantage the earlier the branch prediction is made in the pipeline. For example, fetch based branch prediction is known, which attempts to provide branch prediction prior to the instruction being fully decoded and executed. As such, fetch based branch prediction may include prediction at a fetch stage or each stage in the pipeline.
Several types of branch prediction include, for example, the use of a correlation of previous branches. With dynamic branch prediction, for example, prediction techniques may use a program counter of a branch to index into a branch history table. The index bits that are used may be some bits of the program counter associated with the instruction requiring a branch. However, a problem arises if the index bits of the program counter are the same for multiple addresses. In such an instance, there can be two branches using the same counter so there is an increase in the number of counters required, thereby adding to the size of the die required to fabricate the branch prediction function.
Branch target buffers are also known to be used to facilitate branch prediction. Branch target buffers, as known in the art, may be used in fetch based prediction techniques and typically serve as a table that stores a program counter value that corresponds to instructions having branches. Stored with the program counter value is typically a target address for the branch.
Global branch histories typically include histories of all branches and are used to avoid dual counters. These are typically used after the instructions have been processed and are fed back as actual branch information to use as an index. In addition, multiple level branch predictions are used which may use two tables of data wherein one table may be dedicated for the global history of all branches and another table may be dedicated for the history of a particular branch.
Branch prediction techniques are known for variable length instruction sets, such as the X.86 instruction set, and are widely used in microprocessor technology. However, branch prediction should be performed for each of the multiple different instruction sets to help insure efficient operation when any instruction set is being executed. One way of addressing branch prediction for multiple instruction sets is to duplicate branch prediction related circuits and memory wherein each instruction set may have dedicated branch prediction operations. However, this may unnecessarily increase the cost and reduce the efficiency of the processor.
Consequently, there exists a need for an instruction branch prediction method and apparatus that can efficiently perform branch prediction for multiple instruction sets executed on a multiple instruction set processor.